<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>BFMLAL (multiple and single vector)</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BFMLAL (multiple and single vector)</h2><p>Multi-vector BFloat16 floating-point multiply-add long by vector</p>
      <p class="aml">This BFloat16 floating-point multiply-add long instruction widens all 16-bit BFloat16 elements in the one, two, or four first source vectors and the second source vector to single-precision format, then multiplies the corresponding elements and destructively adds these values without intermediate rounding to the overlapping 32-bit single-precision elements of the ZA double-vector groups. The lowest of the two consecutive vector numbers forming the double-vector group within all of, each half of, or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo all, half, or quarter the number of ZA array vectors.</p>
      <p class="aml">The <span class="arm-defined-word">vector group</span> symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA double-vector groups respectively. The <span class="arm-defined-word">vector group</span> symbol is preferred for disassembly, but optional in assembler source code.</p>
      <p class="aml">This instruction follows SME ZA-targeting floating-point behaviors.</p>
      <p class="aml">This instruction is unpredicated.</p>
    
    <p class="desc">
      It has encodings from 3 classes:
      <a href="#iclass_sme_vgx1_double">One ZA double-vector</a>
      , 
      <a href="#iclass_sme_vgx2_double">Two ZA double-vectors</a>
       and 
      <a href="#iclass_sme_vgx4_double">Four ZA double-vectors</a>
    </p>
    <h3 class="classheading"><a id="iclass_sme_vgx1_double"/>One ZA double-vector<span style="font-size:smaller;"><br/>(FEAT_SME2)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td class="r">0</td><td colspan="4" class="lr">Zm</td><td class="lr">0</td><td colspan="2" class="lr">Rv</td><td class="l">0</td><td>1</td><td class="r">1</td><td colspan="5" class="lr">Zn</td><td class="lr">1</td><td class="lr">0</td><td colspan="3" class="lr">off3</td></tr><tr class="secondrow"><td colspan="12"/><td colspan="4"/><td/><td colspan="2"/><td colspan="3"/><td colspan="5"/><td/><td class="droppedname">S</td><td colspan="3"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bfmlal_za_zzv_1"/><p class="asm-code">BFMLAL  ZA.S[<a href="#sa_wv" title="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a>, <a href="#sa_offsf" title="Vector select offset, pointing to first of two consecutive vectors, encoded as &quot;off3&quot; field times 2 (field off3)">&lt;offsf&gt;</a>:<a href="#sa_offsl" title="Vector select offset, pointing to last of two consecutive vectors, encoded as &quot;off3&quot; field times 2 plus 1 (field off3)">&lt;offsl&gt;</a>], <a href="#sa_zn" title="First source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a>.H, <a href="#sa_zm" title="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a>.H</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
integer v = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(off3:'0');
boolean sub_op = FALSE;
constant integer nreg = 1;</p>
    <h3 class="classheading"><a id="iclass_sme_vgx2_double"/>Two ZA double-vectors<span style="font-size:smaller;"><br/>(FEAT_SME2)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td class="r">0</td><td colspan="4" class="lr">Zm</td><td class="lr">0</td><td colspan="2" class="lr">Rv</td><td class="l">0</td><td>1</td><td class="r">0</td><td colspan="5" class="lr">Zn</td><td class="lr">1</td><td class="lr">0</td><td class="lr">0</td><td colspan="2" class="lr">off2</td></tr><tr class="secondrow"><td colspan="12"/><td colspan="4"/><td/><td colspan="2"/><td colspan="3"/><td colspan="5"/><td/><td class="droppedname">S</td><td/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bfmlal_za_zzv_2x1"/><p class="asm-code">BFMLAL  ZA.S[<a href="#sa_wv" title="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a>, <a href="#sa_offsf_1" title="Vector select offset, pointing to first of two consecutive vectors, encoded as &quot;off2&quot; field times 2 (field off2)">&lt;offsf&gt;</a>:<a href="#sa_offsl_1" title="Vector select offset, pointing to last of two consecutive vectors, encoded as &quot;off2&quot; field times 2 plus 1 (field off2)">&lt;offsl&gt;</a>{, VGx2}], { <a href="#sa_zn1" title="First scalable vector register of a multi-vector sequence, encoded as &quot;Zn&quot; (field Zn)">&lt;Zn1&gt;</a>.H-<a href="#sa_zn2" title="Second scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn2&gt;</a>.H }, <a href="#sa_zm" title="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a>.H</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
integer v = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(off2:'0');
boolean sub_op = FALSE;
constant integer nreg = 2;</p>
    <h3 class="classheading"><a id="iclass_sme_vgx4_double"/>Four ZA double-vectors<span style="font-size:smaller;"><br/>(FEAT_SME2)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td class="r">1</td><td colspan="4" class="lr">Zm</td><td class="lr">0</td><td colspan="2" class="lr">Rv</td><td class="l">0</td><td>1</td><td class="r">0</td><td colspan="5" class="lr">Zn</td><td class="lr">1</td><td class="lr">0</td><td class="lr">0</td><td colspan="2" class="lr">off2</td></tr><tr class="secondrow"><td colspan="12"/><td colspan="4"/><td/><td colspan="2"/><td colspan="3"/><td colspan="5"/><td/><td class="droppedname">S</td><td/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bfmlal_za_zzv_4x1"/><p class="asm-code">BFMLAL  ZA.S[<a href="#sa_wv" title="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a>, <a href="#sa_offsf_1" title="Vector select offset, pointing to first of two consecutive vectors, encoded as &quot;off2&quot; field times 2 (field off2)">&lt;offsf&gt;</a>:<a href="#sa_offsl_1" title="Vector select offset, pointing to last of two consecutive vectors, encoded as &quot;off2&quot; field times 2 plus 1 (field off2)">&lt;offsl&gt;</a>{, VGx4}], { <a href="#sa_zn1" title="First scalable vector register of a multi-vector sequence, encoded as &quot;Zn&quot; (field Zn)">&lt;Zn1&gt;</a>.H-<a href="#sa_zn4" title="Fourth scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn4&gt;</a>.H }, <a href="#sa_zm" title="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a>.H</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
integer v = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(off2:'0');
boolean sub_op = FALSE;
constant integer nreg = 4;</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Wv&gt;</td><td><a id="sa_wv"/>
        
          <p class="aml">Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;offsf&gt;</td><td><a id="sa_offsf"/>
        
          
        
        
          <p class="aml">For the one ZA double-vector variant: is the vector select offset, pointing to first of two consecutive vectors, encoded as "off3" field times 2.</p>
        
      </td></tr><tr><td/><td><a id="sa_offsf_1"/>
        
          <p class="aml">For the four ZA double-vectors and two ZA double-vectors variant: is the vector select offset, pointing to first of two consecutive vectors, encoded as "off2" field times 2.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;offsl&gt;</td><td><a id="sa_offsl"/>
        
          
        
        
          <p class="aml">For the one ZA double-vector variant: is the vector select offset, pointing to last of two consecutive vectors, encoded as "off3" field times 2 plus 1.</p>
        
      </td></tr><tr><td/><td><a id="sa_offsl_1"/>
        
          <p class="aml">For the four ZA double-vectors and two ZA double-vectors variant: is the vector select offset, pointing to last of two consecutive vectors, encoded as "off2" field times 2 plus 1.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zn&gt;</td><td><a id="sa_zn"/>
        
          <p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zn1&gt;</td><td><a id="sa_zn1"/>
        
          <p class="aml">Is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn".</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zn4&gt;</td><td><a id="sa_zn4"/>
        
          <p class="aml">Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" plus 3 modulo 32.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zn2&gt;</td><td><a id="sa_zn2"/>
        
          <p class="aml">Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" plus 1 modulo 32.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zm&gt;</td><td><a id="sa_zm"/>
        
          <p class="aml">Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckStreamingSVEAndZAEnabled.0" title="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
constant integer elements = VL DIV 32;
integer vectors = VL DIV 8;
integer vstride = vectors DIV nreg;
bits(32) vbase = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
integer vec = (<a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
bits(VL) result;
vec = vec - (vec MOD 2);

for r = 0 to nreg-1
    bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[(n+r) MOD 32, VL];
    bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
    for i = 0 to 1
        bits(VL) operand3 = <a href="shared_pseudocode.html#impl-aarch64.ZAvector.read.2" title="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[vec + i, VL];
        for e = 0 to elements-1
            bits(16) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + i, 16];
            bits(16) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * e + i, 16];
            bits(32) element3 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 32];
            if sub_op then element1 = <a href="shared_pseudocode.html#impl-shared.BFNeg.1" title="function: bits(N) BFNeg(bits(N) op)">BFNeg</a>(element1);
            <a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = <a href="shared_pseudocode.html#impl-shared.BFMulAddH_ZA.4" title="function: bits(N) BFMulAddH_ZA(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr)">BFMulAddH_ZA</a>(element3, element1, element2, FPCR[]);
        <a href="shared_pseudocode.html#impl-aarch64.ZAvector.write.2" title="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec + i, VL] = result;
    vec = vec + vstride;</p>
    </div>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
    </p></body></html>
